Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling

Today's DRAM process is expected to continue scaling, enabling minimum feature sizes below 10nm. To achieve this, the main challenges to address are expected to be refresh, write recovery time (tWR), and variable retention time (VRT) parameters. This paper proposes enhancement features that address these three scaling parameters by simultaneously coarchitecting the controller and DRAM instead of designing them individually. Combining temperature compensated tWR (TCWR) with sub-array level parallelism (SALP) enables tWR relaxation, while further improving performance above a given temperature threshold such as 25 o C. In-DRAM ECC enables efficient repairs when refresh and VRT failures generate fail bits. It also provides additional single bit failure protection, thereby increasing field reliability which is critical for servers. Despite the general perception that in-DRAM ECC is not applicable to server main memories due to excessive chip size increases, the proposed inDRAM ECC with dummy data bit pre-fetching results in a modest array size increase of only ~6.2%. By changing the echosystem to enable the proposed features, DRAM scaling is expected to accelerate further, enabling a continuous supply of low cost, high capacity, high performance, and low power DRAMs for the industry.